A single-issue five-stage pipelined CPU implemented in Verilog
verilog
A Verilog online evaluation sandbox that can be used for Online Judge (OJ) development
shell modelsim python
Solutions and documents of HDLBits
A tool for signing and verifying ELF files
openssl ELF
A kernel module for ELF file verification implemented through hooking system calls
Ftrace ELF Kernel
A SSA-based compiler of C subset (extended SysY language)
Compiler Optimization SSA
A toy kernel which is x86 based.
Kernel
A Standard Compliance Analyzer based on Clang
Static Analysis MISRA Compiler
